1. Field of the Invention
The present invention relates to a data processor, particularly, to a data processor which receives interrupt requests and executes a corresponding interrupt process.
2. Description of Related Art
FIG. 1 is a block diagram showing a configuration of a processor and an interrupt control circuit of a conventional data processor.
In the following, an explanation will be made on the configuration and operation for performing interrupt processings in the conventional data processor.
In FIG. 1, reference numeral 101 designates an address bus, 102 a data bus, 103 a memory, 110 a processor, and 130 an interrupt control circuit.
In addition, the memory 103, the processor 110 and the interrupt control circuit 130 are connected with each other through the address bus 101 and the data bus 102.
In the processor 110, an instruction execution control unit 114, a PSW (Processor Status Word) 116 and the like are provided. The signal lines in the processor 110 are omitted.
The instruction execution control unit 114 controls instruction execution and interrupt processing in the processor 110. Specifically, the instruction execution control unit 114 examines, when an instruction execution or an interrupt processing is finished, the state of an interrupt request signal 236, to be described later, is checked for the presence or absence of interrupt requests. When there is an interrupt request, the instruction execution control unit 114 activates the interrupt processing.
The PSW 116 is a register showing the status of the processor 110, in which, as shown in FIG. 2, a processor interrupt priority level field, an interrupt prohibition flag field and the like are set.
In the processor interrupt priority level field, the interrupt priority level possessed by the processor 110 at the present is set. The instruction execution control unit 114 of the processor 110 receives an interrupt request having a higher priority level than the processor interrupt priority level set in the PSW 116 as the interrupt request signal 236.
The value set in the processor interrupt priority level field is supplied as a processor interrupt priority level signal 213 to a maskable interrupt request generation deciding circuit 133 of the interrupt control circuit 130, described hereinafter.
On the other hand, in the interrupt prohibition flag field, an interrupt prohibition flag is set which prohibits receiving a maskable interrupt request when "1" is set, and enables receiving the maskable interrupt request when "0" is set. The set value of the interrupt prohibition flag is supplied as an interrupt prohibition flag signal 214 to the maskable interrupt request generation deciding unit 133 of the interrupt control circuit 130.
The interrupt control circuit 130 is provided with an interrupt level priority judging unit 131, the maskable interrupt request generation deciding unit 133, a non-maskable factor judging unit 134, an interrupt request holding unit 235, an interrupt information register 137, and the like.
The interrupt level priority judging unit 131 judges which interrupt request among EI0, EI1 . . . of the maskable interrupt (EI) is generated and which is the highest interrupt level among requests of the generated maskable interrupts EI0, EIl . . . , and selects any maskable interrupt having the highest interrupt priority level.
Specifically, the interrupt level priority judging unit 131 is provided with a plurality of interrupt control registers 132 (132-0, 132-1 . . . ). To each of the interrupt control registers 132, maskable interrupt request signal 238 (238-0, 238-1 . . . ) showing that there is a request of each of the maskable interrupts EI0, EI1 . . . is supplied. Each of the interrupt control register 132-0, 132-1, . . . is a register for holding the presence or absence of an interrupt request and an interrupt level for each of the factors of the maskable interrupt EI0, EI1 . . . As shown in FIG. 3, an interrupt request bit field and an interrupt priority level field are set in the interrupt control register 132.
When there is any interrupt request from among the maskable interrupts EI0, EI1 . . . , "1" is set in an interrupt request bit in any one of the interrupt control registers 132-0, 132-1, . . . corresponding to the interrupt factor. In each of the interrupt control register 132, an intrinsic address is allocated, thereby it is possible to read/write a value of each interrupt control register 132 from the outside. Therefore, it is possible to set a priority level corresponding to each interrupt factor in advance in the interrupt priority level of each interrupt control register 132.
The maskable interrupt request generation deciding unit 133 receives an interrupt only when the set value of the interrupt prohibition flag supplied from the processor 110 as the interrupt prohibition flag signal 214 is "0" and the priority level of the maskable interrupt (EI) selected by the interrupt level priority judging unit 131 is higher than the processor interrupt priority level supplied as the processor interrupt priority level signal 213, and outputs the interrupt request to the non-maskable factor judging unit 134. But when the set value of the interrupt prohibition flag is "1" and the interrupt priority level selected by the interrupt level priority judging unit 131 is lower than the processor interrupt priority level, the interrupt request is not outputted from the maskable interrupt request generation deciding unit 133 to the non-maskable factor judging unit 134.
The non-maskable factor judging unit 134 outputs, when a non-maskable interrupt (either a watchdog timer interrupt (WDTI) or a debugger exclusive interrupt (DBI)) is given as a WDTI request signal 139 or a DBI request signal 141 is given, the request of the interrupt. That is, the non-maskable interrupts WDTI and DBI always have higher priority than the maskable interrupt (EI) and are not masked by the processor interrupt priority level or interrupt prohibition flag set in the PSW 116. When there is no request of the non-maskable interrupt WDTI or DBI, the non-maskable factor judging unit 134 outputs intact the interrupt request of the maskable interrupt (EI) given from the aforesaid maskable interrupt request generation deciding unit 133.
The interrupt request holding unit 235 holds an information showing the presence or absence of an interrupt request given from the non-maskable factor judging unit 134, and outputs the value to the instruction execution control unit 114 of the processor 110 as the interrupt request signal 236.
The interrupt information register 137 holds a priority level, vector address, or the like, of the interrupt and sends interrupt request to the processor 110. An intrinsic address is allocated to the interrupt information register 137, and the content can be read from the outside of the interrupt control circuit 130, for example, from the processor 110.
In the following, an explanation will be given on the operation of the interrupt control circuit 130.
The interrupt level priority judging unit 131 selects a request of the highest priority level from among the maskable interrupts EI0, EI1, . . . having interrupt requests by referring to contents of the interrupt control registers (132-0, 132-1 . . . ), and outputs the vector address and the interrupt priority level of the selected request to the maskable interrupt request generation deciding unit 133.
At the maskable interrupt request generation deciding unit 133, the interrupt priority level given from the interrupt level priority judging unit 131 is compared with the processor interrupt priority level signal 213 showing the processor interrupt priority level set, at that time, in the PSW 116 of the processor 110. When the given interrupt priority level is higher than the processor interrupt priority level, the maskable interrupt request generation deciding unit 133 receives the interrupt. When the interrupt is received, the maskable interrupt request generation deciding unit 133 outputs an interrupt request as well as the vector address and the interrupt priority level thereof to the non-maskable factor judging unit 134.
The non-maskable factor judging unit 134 outputs, when there is a request of a debugger exclusive interrupt (DBI) or a watchdog timer interrupt (WDTI), the interrupt request as well as a vector address and an interrupt priority level (=0) thereof. But when there are both requests, the debugger exclusive interrupt (DBI) is received prior to the watchdog timer interrupt (WDTI). When there is no request, the non-maskable factor judging unit 134 outputs intact a value sent from the maskable interrupt request generation deciding unit 133 to the interrupt request holding unit 235.
The presence or absence of an interrupt request is temporarily held in the interrupt request holding unit 235, and the value held in the interrupt request holding unit 235 is outputted to the processor 110 as the interrupt request signal 236. In addition, the vector address and the interrupt priority level are inputted from the non-maskable factor judging unit 134 to the interrupt information register 137 and held therein.
In the following, an explanation will be made on the operation of the processor 110.
Every time an instruction execution is finished or every time an interrupt processing is finished, the instruction execution control unit 114 examines the interrupt request signal 236 given from the interrupt control circuit 130 to detect the presence or absence of an interrupt request, and activates an interrupt processing when there is an interrupt request.
As per the interrupt processing done by the instruction execution control unit 114 of the processor 110, all of the following processings are performed by the hardware control.
(1) Reading of the interrupt information register
When an interrupt request is received, the instruction execution control unit 114 reads a content of the interrupt. information register 137 by using the address bus 101 and the data bus 102.
In addition, when the value of the interrupt information register 137 is read by the information execution control unit 114, an interrupt request bit of the interrupt control register 132 corresponding to the received interrupt factor is cleared to be "0" in the interrupt level priority judging unit 131.
(2) Saving of a processor information to a stack
The instruction execution control unit 114 saves such processor informations as a value of the PSW 116 (hereinafter to be called a PSW value) and a value of a program counter (not shown) (hereinafter to be called a PC value) to a stack set in the memory 103.
(3) Updating of a PSW value
The instruction execution control unit 114 sets the interrupt prohibition flag of the PSW 116 whose content has been saved temporarily to the stack by the processing of (2) to "1", as well as the substitute of the processor priority level for the received interrupt priority level.
In addition, since both of the above are given to the maskable interrupt request generation deciding unit 133 as the interrupt prohibition flag signal 214 and the processor interrapt priority level signal 213, respectively, the maskable interrupt request generation deciding unit 133 decides whether to receive or not receive the maskable interrupts (EI) according to these signals.
(4) Acquisition of a start address of an interrupt handler
A software program performing a processing corresponding to an interrupt factor is an interrupt handler.
The instruction execution control unit 114 acquires a start address of-the interrupt handler by reading the memory 103 with the vector address as a read address obtained before from the interrupt information register 137.
(5) Activation of interrupt handler
The instruction execution control unit 114 jumps the processing sequence to the start address of the interrupt handler obtained by the processing of (4). However, also at this time, the interrupt request, signal 236 is checked by the instruction execution control unit 114.
When an interrupt handler is executed by the fact that a return instruction from the interrupt handler is executed at the previous execution, the instruction execution control unit 114 makes the PSW value, and the PC value which have been saved in the stack in advance return, respectively, to the PSW 116 and PC (not shown), to return to the state before the interrupt.
As aforementioned, when an interrupt request is received, the conventional data processor prohibits to receive, by making the interrupt prohibition flag become "effective", all of the other interrupt requests having priority levels. This interrupt prohibition state continues until the interrupt prohibition flag is cleared by the interrupt handler processed at that time.
But the interrupt prohibition flag is effective only to the maskable interrupts EI0, EI1 . . . which are interrupt requests having priority levels. That is, the ones which are not received when the interrupt prohibition flag is set are only the maskable interrupts EI0, EI1 . . . having priority levels. Therefore, such interrupt requests as, such as the debugger exclusive interrupt (DBI), the watchdog timer interrupt (WDTI), and the like, having no priority level, are received even when the interrupt prohibition flag of the PSW 116 is set. In other words, an interrupt request having no priority level is always received.
As aforementioned, when an interrupt (maskable interrupt) request having a priority level is received, the conventional data processor is prohibited to receive by making the interrupt prohibition flag become "effective" in the interrupt processing, when all of the other interrupt requests have priority levels. Therefore, even when an interrupt request having higher priority level is generated while an interrupt processing is performed according to a certain interrupt request, the former interrupt request is not received immediately after the interrupt processing, but has to wait until the interrupt prohibition flag is made "ineffective" by the processing of the interrupt handler.
The conventional data processor is constructed to receive an interrupt (non-maskable) request having no priority level, and is not constructed to prohibit to receive it. Therefore, when a plurality of interrupt requests having no priority level is generated at the same time, after one interrupt processing is finished, another interrupt processing is immediately activated to perform a multi-interrupt processing.
Therefore, a conventional data processor capable of receiving a plurality of interrupts having no priority level such as a conventional interrupt for debugger has to perform interrupt processing with due regard to a multi interrupt processing, and the control method becomes complicated.